#Sr. principal software engineer trial
Junior Developer: through trial and error.
#Sr. principal software engineer drivers
Founding member of the development team for Solaris PCI-Express Software Stack for Sun's SPARC and Intel Systems Led the design and development for Solaris PCI-Express Framework including SPARC and Intel PCI-Express Root-Complex, PCI-Express Switch and Bridge drivers Led the design and development for Solaris Interrupt Framework to support PCI-Express interrupts MSI, MSI-X, INTx and Messages including NUMA (device locality) based interrupt assignment and distribution and Solaris DDI interrupt interfaces for device drivers Led architecture, design and development for Solaris DMA Framework to support SPARC PCI-Express Root-complex ATU hardware (Multiple TSBs, Large IOMMU pages) including Solaris DDI DMA interfaces Led the design and development for Solaris Hotplug Framework including Virtual hotplug feature used to support IO Virtualization (PCIe Bus, Slot and VF assignments) Lead engineer responsible for majority of PCI-Express Hardware Bringup on all Sun's SPARC and Intel Servers and Workstations.Senior Staff Engineer Zendesk － KS, State Led architecture, design and development of Solaris and SR-IOV support for LDOMs and Solaris Kernel Zones virtualizations for SPARC and Intel systems including design and development for SR-IOV NIC, Fiber Channel and Infiniband devices.Plus, lead software design and development for these features Led architecture, design and development of Solaris, and SPARC Logical Domains (LDOMs) support for Dynamic PCIe Bus Assignment to support multiple Root-domains Involved in the definition or direction of IO Resiliency (High Availability) feature for LDOMs that allows rebooting of PCIe Fabric owner while a VM with an SR-IOV VF continue to run.Worked on PCI-Express FMA Case Study for Oracle Platforms, identified all PCIe/IO FMA gaps and presented to wider engineering and management teams Lead engineer responsible for PCI-Express Hardware bringup and all Solaris IO software development for SPARC M7/T7 Systems Worked with Hardware team on new SPARC Interrupt Architecture based on priority based Event Queues (EQ) to deliver MSI/Xs, PCIe TLP Processing Hints and Atomics Ops features for SPARC M7/T7 Systems.Plus, exploring options to support PCI-Express QOS and ATS features for improved IO performance for Cloud Applications Worked with Hardware team to architect and design new SPARC PCI-Express Root-Complex to support NVMe surprise removal using PCIe DPC feature, IO Cache Scaling, DTU (IO Accelerator), SR-IOV IO Exerciser and Error Injector hardware.Working with Hardware team to architect and re-design next generation SPARC PCI-Express Root- Complex hardware for better error isolation to support high availability for Oracle Engineering and Cloud Platforms.Senior Principal Software Engineer Rtx － Indian Hills, CO
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